TakeMS BD1024TEC860 Scheda Tecnica
Navigare online o scaricare Scheda Tecnica per Moduli di memoria TakeMS BD1024TEC860. takeMS DDR400 ECC reg., 1GB Manuale Utente
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takeMS BD1024TEC860
Features
184-pin registered DDR SDRAM
JEDEC Standard 184pin DIMM 2.5V +/- 0.2V VDD & VDDQ Power supply
Auto Refresh (CBR) and Self Refresh Mode
Programmable Burst Length
Fully differential clock operations
Serial Presence Detect (SPD) with EEPROM
Module layout is based on JEDEC standard routing guidelines
Impedance controlled 6-layer PCB Technology
JEDEC standard form factor
Internal four bank operations
single pulsed data for write RAS
Operating Temperature 0°C ~ 75°C
Description
These Memory devices are JEDEC standard registered
DIMM modules, based
on CMOS DDR SDRAM technology.
These devices consist of CMOS DDR SDRAMs in TSOP or FBGA packages on
a 184-pin glass epoxy substrate.The memory array is designed with Double
Data Rate (DDR) Synchronous DRAMs for server applications.
The pipelined, multibanked architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high, effective bandwidth.
Decoupling capacitors are mounted on the PCB board in parallel for each
DDR SDRAM, which provides proper voltage supply impedance over the
whole frequency range of operations, in accordance with JEDEC
specifications. These modules feature Serial Presence Detect (SPD) based
on a serial EEPROM device.
1
2
Sommario
Pagina 1 - Description
takeMS BD1024TEC860 Features 184-pin registered DDR SDRAM JEDEC Standard 184pin DIMM 2.
Pagina 2 - Technical details
Technical details - 1024 MB longdimm module - 128Mx4 IC organisation - x72 module organisation - 400MHz / PC 3200 - double sided / 16 ICs (+E
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| TROJAN T15 Tongue Operated Guard Interlock Switch |
User Manual
Rockwell Automation TROJAN T15 Tongue Operated Guard Interlock Switch User Manual,
1 pages |
| TWT10XZO Triplicated Watchdog Timer |
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